Prior art devices implemented a set of memory mapped control registers called memory attribute registers. These registers defined the cacheability of external addresses in the Level one and Level two caches inside the memory system. The entire external address space was controlled by 256 memory address registers. Each memory attribute register defined the cacheability of a corresponding portion of the address space.
In prior art devices, the memory attribute registers were not visible in the level one data cache controller. Due to this, the following performance optimizations that level one data cache controller could have implemented were not possible: merge writes for external addresses based on the cacheability of accesses; optimize some of its cache state machines based on early knowledge of cacheability; and the level one data cache controller must generates and send victims due to read accesses even to non-cacheable external addresses.